The present invention relates to a clock generation circuit for generating internal clock signals synchronized with external clock signals, and a clock generation circuit using a DLL (Delay Locked Loop) circuit or an SMD (Synchronous Mirror Delay) circuit. The present invention also relates to a technology effective for application to a clock generation circuit for generating clock signals each used to determine output timing in an SDRAM (Synchronous Dynamic Random Access Memory), for example.
In recent years, attention has been given to a DDR (Double Date Rate) type SDRAM for performing the input/output of data at a speed twice that for each of input clocks as means for speeding up a data transfer rate of the SDRAM. It has been examined that the DDR SDRAM is equipped with a clock reproducing circuit called a xe2x80x9cDLL (Delay Locked Loop) or SMD (Synchronous Mirror Delay)xe2x80x9d to perform the input/output of data at high speed, thereby causing the phase of each of external clocks and that of a data output to coincide with each other. This is done to sufficiently ensure the time required to set up the output data with respect to the external clock. When the phase of the external clock and that of the data output coincide with each other, the time required between the input of a read command and the output of data might be an integral multiple of the cycle of the external clock.
In the DLL circuit or the SMD circuit, each of clocks, which is inputted from a clock input terminal and amplified to a CMOS level by an input first-stage circuit, is caused to pass through a variable delay circuit to thereby generate an internal clock having a desired phase. The internal clock drives a data output latch and the latched data is outputted to the outside through an output buffer. The phase of the internal clock is set so that the phase of the output data coincides with or corresponds to that of the external clock. A type for controlling a delay amount of the variable delay circuit, which is used to determine the phase of the internal clock, by a feedback loop is called xe2x80x9cDLLxe2x80x9d, whereas a type for determining a delay amount by a delay amount measuring circuit is called xe2x80x9cSMDxe2x80x9d.
Unexamined Patent Publication Nos. Hei 11(1999)-225067 and Hei 10(1998)-126254 respectively disclose a semiconductor device including a clock reproducing circuit which has the function of delaying each of external clocks according to its cycle while automatically switching or selecting the number of clock cycles from the external clock to an internal clock according to a clock cycle time to generate the internal clock, thereby making it possible to reduce a circuit scale and stop its operation at standby, reducing an error relative to the external clock, and providing a wide operating frequency range and a frequency doubling function. Unexamined Patent Publication No. Hei 10(1998)-79663 discloses an internal clock signal generation circuit for generating an internal signal phase-synchronized with an external signal through the use of voltage-controlled delay elements, wherein offsets are selectively given to delay times through the voltage-controlled delay elements, whereby it can reliably be locked over a wide frequency domain. Unexamined Patent Publication No. Hei 11(1999)-266239 discloses a clock synchronous delay control circuit which allows delay amounts of delay lines at respective portions of the circuit to be switched over, thereby making it possible to expand an operating frequency band. Unexamined Patent Publication No. Hei 11(1999)-112308 discloses a synchronous delay circuit device which controls the entire delay time of a delay circuit sequence or array according to the results of device states by the measurement of the frequency of an external clock, the measurement of a source voltage to be used, the measurement of device variations in chip, etc., thereby preventing running-off of the clock or its edge from a first-stage delay circuit sequence or array even when used at a low frequency, whereby it properly operates and ensures a suitable delay time, and is configured in a small scale as a result thereof.
It is expected that the above-described SDRAM will be required of a further speeding-up from now on with the speeding-up of a CPU. However, the more the SDRAAM is speeded up, the more power consumption increases. When the form of usage of the SDRAM is taken into consideration, it is also necessary to operate the SDRAM at high speed when the CPU is performing computations or the like. However, when the CPU does not perform the computations, it is not necessary to operate the SDRAM at high speed. Further, the cycle of a clock is extended to operate the SDRAM at low speed, thereby making it possible to restrain or control power consumption.
In the conventional SDRAM using the DLL or SMD, however, the number of delay clock cycles from the input of the read command to the output of the data was kept constant. A frequency range (clock cycle range: hereinafter called a xe2x80x9clock rangexe2x80x9d) of an external clock, in which the DLL or SMD is capable of outputting each clock having a desired phase, was determined according to the performance of a variable delay circuit and a phase difference (hereinafter called a xe2x80x9cclock access timexe2x80x9d) between the external clock corrected by a clock generation circuit and output data.
Assuming that, for example, the minimum delay amount of the variable delay circuit is defined as tdmin, the maximum delay amount thereof is defined as tdmax, the clock access time is defined as tca, and the number of delay cycles from the input of the read command to the output of the data is defined as n, respectively, the minimum period or cycle of the external clock and the maximum period or cycle thereof are given as follows:
Minimum cycle of external clock=(tdmin+tca)/n
Maximum cycle of external clock=(tdmax+tca)/n
As evident as viewed from the above equations, when the performance of the variable delay circuit, i.e., tdmin and tdmax are assumed to be constant, the maximum cycle of the external clock will decrease when an attempt is made to increase n for the purpose of speeding up the SDRAM and thereby reduce the minimum cycle of the external clock. When an attempt is made to reduce n for the purpose of decreasing the speed thereof and thereby increase the maximum cycle, the minimum cycle of the external clock will increase. Thus, a delay variable range of the variable delay circuit must be increased to make it possible to lower the allowable minimum cycle of the external clock and increase the allowable maximum cycle of the external clock.
However, a problem arises in that when an attempt is made to do so in the conventional circuit format or type as it is, the number of stages for delay gates must be increased, so that the variable delay circuit increases in circuit scale, thereby resulting in an increase in its occupied area and an increase in power consumption.
An object of the present invention is to provide a clock generation circuit relatively small in circuit scale and having a wide lock range. The above, other objects and novel features of the present invention will become apparent from the description of the present invention and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be explained in brief as follows:
A variable delay circuit is used in the case of DLL, and a delay amount measuring circuit is used in the case of SMD. In a start sequence specified by an MRS (Mode Register Set) command or the like, the corresponding circuit is configured so as to be capable of measuring the optimum number of cycles for a delay amount from the input of an external clock to the output of data and performing lock according to the measured number of cycles, whereby a clock generation circuit having a wide lock range can be implemented regardless of the performance of the variable delay circuit and a clock access time.
More specifically, in a clock generation circuit comprising at least one input terminal, at least one output terminal, fixed delay applying means which applies a predetermined delay corresponding to a time from the time at which a signal is inputted to the input terminal, to the output of a signal from the output terminal, a variable delay circuit comprising a combination of one or more variable delay elements each having a delay time control terminal, a phase detector which detects a phase difference between a signal prior to being inputted to the variable delay circuit and a signal delayed by the variable delay circuit and the fixed delay applying means, delay amount control means which controls a delay amount developed in the variable delay circuit according to the phase difference detected by the phase detector, and number-of-cycles control means which determines the number of clock cycles for a delay from the input of the signal to the variable delay circuit to the execution of the phase comparison by the phase detector, the delay amount control means controls the delay amount of the variable delay circuit according to the number of clock cycles determined by the number-of-cycles control means.
Alternatively, in a clock generation circuit comprising at least one input terminal, at least one output terminal, fixed delay applying means which applies a predetermined delay corresponding to a time from the time at which a signal is inputted to the input terminal, to the output of a signal from the output terminal, a variable delay circuit comprising a combination of one or more variable delay elements each having a delay time control terminal, a phase detector which detects a phase difference between a signal prior to being inputted to the variable delay circuit and a signal delayed by the variable delay circuit and the fixed delay applying means, delay amount control means which controls a delay amount developed in the variable delay circuit according to the phase difference detected by the phase detector, and number-of-cycles control means which determines the number of clock cycles for a delay from the input of the signal to the variable delay circuit to the execution of the phase comparison by the phase detector, the number-of-cycles control means inputs an external clock signal or a test signal synchronized with the external clock signal and having a predetermined delay to the variable delay circuit, and observes a signal obtained from a predetermined delay stage of the variable delay circuit to thereby determine the optimum number of clock cycles, and thereafter the delay amount control means controls the delay amount of the variable delay circuit according to the number of clock cycles determined by the number-of-cycles control means.
According to the above means, the number of the clock cycles is reduced when the cycle of each clock is long, whereas the number of the clock cycles increases when the cycle thereof is long. Thus, a clock generation circuit having a wide lock range can be implemented using a variable delay circuit relatively narrow in delay amount variable range as compared with the case where the number of the clock cycles is fixed.
The fixed delay applying means provides a fixed delay corresponding to the sum of a delay developed in a signal path from the input terminal to the variable delay circuit and a delay developed in a signal path from the variable delay circuit to the data output terminal, for a signal inputted thereto. Thus, an output clock synchronized with each clock signal inputted from the outside can be produced.
The variable delay circuit comprises a plurality of variable delay elements connected in series. In the variable delay circuit, the number of stages for the variable delay elements through which the input signal passes up to the output thereof, is controlled to vary the delay amount of the variable delay circuit. Owing to the series-connection of the plurality of variable delay elements, control on a delay amount by the selection of the number of stages for the delay elements can be performed in addition to control on a delay amount developed in one variable delay element. Therefore, a delay amount variable range of the variable delay circuit becomes wide.
Further, there is provided number-of-cycles control means which controls the number of clock cycles for a delay amount from the input of the variable delay circuit to the output of the fixed delay circuit, based on a signal outputted from the variable delay circuit. It is therefore possible to automatically detect the optimum number of clock cycles and control a delay amount based on it.
Furthermore, there is provided means which generates a signal or voltage for controlling the delay amount of the variable delay circuit according to the phase difference detected by the phase detector. It is thus possible to perform an automatic phase coincidence or adjustment based on a feedback loop.
Still further, there is provided a first divider provided in a stage preceding the phase detector, which divides a signal prior to being inputted to the variable delay circuit. The first divider is configured so as to output signals different in phase by a clock cycle, according to the number of the clock cycles determined by the number-of-cycles determining means. It is thus possible to avoid lapsing into a harmonic lock state due to a phase comparison between improper signal edges.
The delay amount control means includes filter capacitors each of which generates a voltage corresponding to the phase difference detected by the phase detector. The filter capacitors may preferably have capacitance values varied according to the number of stages for the variable delay elements through which the signal inputted to the variable delay circuit passes up to the output thereof. It is thus possible to avoid the rate of control on a delay amount to the voltage corresponding to the phase difference from varying due to the difference in the number of delay stages activated in the variable delay circuit, and make rapid transition to a phase-locked state.
Further, in a semiconductor memory device provided with such a clock generation circuit as described above, a clock signal supplied from the outside is inputted to the clock generation circuit to generate a clock signal, and data is outputted with the generated clock signal as a timing signal, whereby a semiconductor memory device can be implemented which is short in clock access time and long in setup time.